VOID-FREE Cu FILL · Ti/Cu SEED LAYER · SEM CROSS-SECTION · NANOSYSTEMS JP INC.
At Nanosystems JP Inc., we offer Through-Glass Via microfabrication for 2.5D/3D packaging, RF MEMS, photonics, and biomedical devices. Precision diameters from 20µm, panels to 510×510mm, and via yield exceeding 95%.
TGVs play an important role in advanced wafer packaging. Glass offers distinct advantages over silicon, especially for RF applications, optical devices, and scenarios where CTE matching with organic substrates is critical.
Industry-leading control over via geometry, diameter, shape, and depth all customisable to your design requirements.
Via shape is selected based on diameter requirements and application, each offering different filling characteristics and mechanical properties.
From standard wafer formats to large-panel production, one fabrication partner for prototyping and volume.
Five glass types covering RF, optical, display, and high-durability applications, each with distinct electrical and thermal properties.
Ti/Cu seed layer + Cu electroplating for conformal or void-free fill. Low resistance. High via yield exceeding 95%.
Beyond via formation, full substrate finishing services coordinated in the same project flow.
After via formation, copper metallisation is applied using an advanced Ti/Cu seed layer followed by electroplating. Two fill modes are available depending on your electrical and structural requirements. Completely filled vias offer lower resistance and direct thermal conduction. Conformal vias coat the sidewalls while leaving a hollow core - suited for RF shielding structures and applications where fill is not required.
High aspect ratio hollow vias: When copper fill is not required, glass TGV holes alone can achieve aspect ratios of 20:1 as a standard target, and up to 100:1 in optimised process conditions. The Cu fill constraint is the limiting factor for high-AR vias - the via geometry itself is not. This makes hollow high-AR TGV practical for optical through-apertures, fluid channels, vent holes in hermetic packages, and coaxial RF via structures where only a conformal sidewall coating is needed.
Thin Cu coating on via sidewalls and base - hollow core remains. Faster plating cycle, lower Cu consumption. Suitable where conductivity rather than void-free fill is the priority: RF shielding coaxial vias, signal routing where resistance spec allows hollow geometry.
Solid dense Cu plug filling the entire via volume, void-free verified by SEM cross-section. Lowest electrical resistance and highest thermal conductivity. Required for 3D-IC interposers, power delivery vias, and any application where via yield reliability and signal integrity are critical.
All parameters can be customised for your specific application. Contact our engineers to discuss requirements outside the ranges listed.
| Parameter | Specification | Notes |
|---|---|---|
| Min via diameter | 20µm | Smaller possible on request |
| Via diameter variation | Multiple diameters on same substrate | Different diameters front/back possible (e.g. 30µm / 60µm) |
| Via shapes | Hourglass, Straight, Tapered | Shape depends on diameter and application |
| Aspect ratio | Up to 1:10 | Higher AR on request for select glass types |
| Substrate sizes | 100mm, 200mm, 300mm wafers; up to ~510×510mm panels | Non-standard sizes available |
| Ultra-thin substrate | Down to 50µm | Requires carrier handling |
| Blind Glass Vias (BGV) | Available | Single-side via for partial depth interconnect |
| Glass types | Borosilicate, Soda lime, Fused silica, Sapphire, Non-alkaline | See glass comparison below |
| Cu fill type | Void-free fill or conformal coating | Void-free recommended for low resistance |
| Seed layer | Ti/Cu by sputtering | Ensures adhesion and plating uniformity |
| Via yield | >95% | Measured post-fill before CMP |
| Cu CMP | Available | Planarises surface for RDL or bonding |
| Optical polishing | Optical-level CMP | For photonic and optical applications |
| RDL | Both-side RDL on TGV substrate | Polymer passivation or Cu damascene |
| Anodic bonding | Available | Glass-to-silicon wafer bonding service |
| Thin film metallisation | Available | Sputtering, e-beam evaporation, ALD |
Use these rules when designing your TGV interposer layout. Parameters outside these ranges are possible on inquiry - contact our engineers with your specific requirements before taping out.
| Parameter | Min | Typical | Max / Notes |
|---|---|---|---|
| Via diameter | 20µm | 50–100µm | Smaller on request; larger → lower aspect ratio |
| Via pitch | 2× via diameter | 150–300µm | Min spacing = 1× via diameter (wall-to-wall) |
| Via wall-to-wall spacing | 1× via diameter | 50–200µm | Tighter possible with straight-wall vias |
| Via-to-edge clearance | 200µm | 500µm | From via centre to substrate edge |
| Via-to-via diameter mismatch | - | - | Multiple diameters on same substrate OK; front/back differ e.g. 30µm / 60µm |
| Aspect ratio (depth ÷ diameter) | 1:1 | 5:1 | Up to 10:1 (Cu-filled). Hollow / unfilled vias: 20:1 typical, up to 100:1 achievable - no Cu fill constraint on aspect ratio |
| Glass substrate thickness | 50µm | 300–500µm | Thinner requires temporary carrier bonding |
| Cu land pad diameter | Via ø + 20µm | Via ø + 50µm | Applies on both sides for void-free fill |
| RDL line width / space | 10µm / 10µm | 20µm / 20µm | Polymer passivation or Cu damascene |
| RDL to via pad keepout | 10µm | 20µm | From RDL edge to land pad edge |
| Solder bump pitch (on TGV RDL) | 100µm | 150–300µm | C4 SnAg or AuSn bumping available after RDL |
| Panel dicing street width | 100µm | 200µm | For panel format (up to 510×510mm) |
Via shape is determined by the formation method and glass type. Hourglass and straight are the most common; tapered suits certain deposition requirements; Blind Glass Vias (BGV) penetrate only partway through the substrate for single-sided interconnects, depth sensors, and optical windows.
Dual-sided inward taper formed by laser drilling from both sides. Ideal for RDL routing where slight taper aids conformal metal coverage. Most common shape for standard TGV interposers.
Perfectly vertical sidewalls for maximum packing density and tightest via pitch. Requires precise laser parameter control. Best choice for high-density interconnect arrays.
Unidirectional conical profile, wider at entry, narrower at exit. Provides easier metal seed layer coverage and more reliable conformal or void-free Cu fill for larger diameter vias.
Partial penetration - via is drilled only partway through the glass substrate without breaching the bottom plane. Used for single-sided interconnects, optical windows, depth sensors, and capacitive structures requiring a closed bottom.
Each glass type brings distinct electrical, optical, thermal, and mechanical properties. We can advise on the best choice for your specific application.
High resistivity. Low electrical loss. Adjustable CTE, better match with organic substrates than silicon. Low-loss tangent for RF.
Cost-effective for large-panel production. Standard display glass composition. Available in the largest panel formats.
UV to IR optical transparency. Minimal electrical loss. Highest thermal stability. Ideal for photonic and optical interposers.
Extreme hardness (Mohs 9). High thermal conductivity. Chemical resistance. For demanding environments requiring robustness.
Very low alkali content. Minimized ion migration. Improved electrical properties for high-frequency and precision applications.
| Property | Glass (TGV) | Silicon (TSV) |
|---|---|---|
| Electrical resistance | Very high (insulator) | Semiconductor (variable) |
| RF / HF loss | Very low (low-loss tangent) | Higher substrate loss |
| CTE match (organic PCB) | Better match (adjustable) | Larger mismatch |
| Optical transparency | Yes (visible to UV/IR) | Opaque (visible light) |
| Large panel format | Yes (up to 510×510mm) | Limited to wafer sizes |
| Cost (large volume) | Lower (panel format) | Higher per unit area |
From bare glass substrate to Cu-filled, planarised vias ready for RDL and bumping, all steps managed as one project.
Vias are formed in the glass substrate using laser ablation or sandblasting, creating the precise diameter and shape profile required. Diameter, shape, and pitch are defined at this stage.
Via sidewalls and substrate surfaces are cleaned and conditioned to ensure excellent adhesion of the subsequent seed layer. Surface roughness is controlled for optimal plating.
Titanium adhesion layer followed by copper seed layer deposited by sputtering. Conformal coverage into via sidewalls is critical for uniform electroplating. High step coverage achieved.
Copper electroplating fills the vias completely (void-free) or conformally. Optimized plating chemistry and parameters ensure consistent fill quality and via yield exceeding 95%.
Chemical mechanical polishing removes excess copper from the substrate surface, creating a flat, smooth surface with exposed via tops. Optical-level polishing available for photonic applications.
Post-CMP processing: Redistribution Layer (RDL) fabrication on one or both sides routes electrical connections. Thin film metallisation, anodic bonding with silicon, and further packaging steps available.
Two Cu fill methods are available depending on your via diameter, aspect ratio, and electrical requirements. Both use Ti/Cu seed + electroplating.
Complete Cu fill from bottom up. Lowest resistance. Best for high-current and signal integrity applications. Via yield >95%.
Cu coats via sidewalls and bottom. Lower Cu volume. Suitable for RF shielding and impedance-controlled via structures.
We offer RDL fabrication on both sides of TGV glass substrates, enabling dense fan-out routing for advanced packaging. Two process routes available:
From advanced semiconductor packaging to biomedical lab-on-chip, TGV glass substrates serve a uniquely broad range of high-performance applications.
Glass interposer chips for cost-effective 2.5D and 3D wafer packaging. Lower cost per unit area than silicon interposers in large panel format.
Low-loss RF substrates for mmWave and 5G. RF MEMS switches, resonators, and filters on high-resistivity glass with minimal substrate loss.
High-density glass interposers for AI accelerators, HPC memory stacking, and chiplet integration with tight pitch via arrays.
Optical transparency enables photonic integration. TGV glass interposers for silicon photonics packaging, optical coherence, and wafer-level optics.
Large panel TGV for display driver interconnects. Enables finer pixel pitch and reduced bezel in next-generation flat panel displays.
BGV (Blind Glass Via) arrays for single-cell experiments. Microfluidic glass chips with integrated TGV electrical connections.
Glass microfluidic chips with TGV electrical feedthroughs, combining microfluidics with integrated sensing and actuation electronics.
Glass shadow masks as an alternative to metal masks for deposition patterning. TGV glass substrates for LED thermal management.
Hermetic glass-silicon MEMS packaging using anodic bonding. TGV provides electrical feedthroughs through the glass cap layer without breaking the seal - a core requirement for vacuum-packaged resonators and inertial sensors.
Fused silica TGV substrates for wafer-level lens arrays, optical sensors, and miniaturised camera modules requiring UV transparency.
Precision glass shadow masks for thin film deposition patterning, an alternative to fragile metal masks for large-area deposition.
Glass cap wafers with TGV electrical feedthroughs for MEMS pressure sensors, accelerometers, and gyroscopes in hermetic packages.
Through-glass vias in fused silica or borosilicate substrates are a well-established route for creating hermetic electrical feedthroughs in MEMS and sensor packages. The sealed cavity protects sensitive moving elements - resonators, pressure membranes, accelerometer proof masses - from atmospheric moisture, particulates, and pressure variations over the device lifetime.
TGV vias filled with Cu or conductive metal provide low-resistance electrical paths through a glass cap wafer while maintaining the seal between the device cavity and the outside environment. Used in MEMS resonators, inertial sensors, and pressure sensors requiring controlled internal atmospheres.
Fused silica offers low thermal expansion closely matched to silicon, good chemical resistance, and optical transparency for inspection and laser-based trim operations. We supply fused silica cap wafers with pre-drilled TGV patterns ready for bonding to the MEMS device wafer.
TGV cap wafers are typically combined with anodic bonding (glass-to-Si) or glass frit bonding to complete the hermetic seal. Nanosystems JP Inc. coordinates the full sequence - TGV substrate supply, via formation, and wafer-level bonding - through one project.
Real samples and process photographs fabricated at Nanosystems JP Inc.
When a device package requires both electrical signal routing and a hermetically sealed cavity - such as a vacuum-packaged MEMS resonator or an optoelectronic module - TGV in fused silica provides the feedthrough path through the glass cap layer without compromising seal integrity. The approach combines TGV formation in a fused silica wafer with a subsequent wafer-level bonding step, creating a sealed enclosure with embedded via connections.
A fused silica or borosilicate glass wafer is drilled with TGV, filled with copper, and then bonded onto the device wafer as the package cap. Electrical signals pass through the glass without any gap in the hermetic boundary - the via metal is co-sealed during bonding.
Fused silica's broad UV-to-IR transmission makes it suitable for optical sensor packages where light must pass through the cap layer - LIDAR windows, IR detector covers, and wafer-level camera modules - while TGV provides the electrical connections on the same substrate.
For MEMS devices requiring a stable vacuum or inert-atmosphere cavity, fused silica offers low gas permeability and minimal outgassing compared to polymer-based or metal cap materials. Combined with anodic bonding, it maintains cavity conditions over the device operating life.
Process coordination note: We supply the fused silica wafer, form the TGV, and coordinate the bonding step as a single project. If your design requires RDL or metal redistribution on the glass cap as well, that can be included in the same process flow. Contact us with your cap layer drawing and we will confirm the full process sequence.
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.
