TSV (Through Silicon Vias) Reveal

At Nanosystems JP, we offer advanced wafer thinning and TSV reveal services using a temporary carrier wafer approach. This process ensures mechanical stability during thinning and enables precise exposure of Through-Silicon Vias (TSVs) for subsequent processing. The typical process flow includes:

1. Temporary Bonding to Carrier Wafer

The device wafer is bonded to a rigid carrier wafer using a temporary adhesive layer/film, enabling safe handling during thinning operations.

2. Backgrinding

The bonded wafer is thinned from the backside through mechanical grinding, reducing the wafer thickness and approaching the TSV tips.

3. Silicon Dry Etching

A controlled dry etching step is used to precisely expose the TSVs without damaging surrounding structures, ensuring vertical access to the via contacts.

4. SiN/SiO₂ Deposition

After TSV exposure, dielectric layers (such as SiN and SiO₂) are conformally deposited to insulate and protect the revealed structures.

5. Chemical Mechanical Planarization (CMP)

CMP is used to planarize the dielectric surface and expose the tops of the TSVs, resulting in a smooth, ready-to-process wafer surface.

This process is ideal for 3D integration, interposer fabrication, and advanced packaging applications.