From GDSII to Diced Chip: The Seamless Path to Hardware Innovation
Nanosystems JP Inc. provides end-to-end semiconductor, MEMS, and nano-fabrication support, from substrate sourcing and mask preparation through front-end processing, advanced packaging, dicing, and final delivery. Projects range from single-process engagements to coordinated multi-step fabrication flows.
20+
20+ Process capabilities
100+
Depositable materials
2″-12″
Wafer size range
550×650mm
Max substrate size
End-to-End Process Coverage
Core Semiconductor Processes
Substrate
& Wafers
& Wafers
Si, Glass, SiC, GaN
→
Design &
Mask
Mask
GDS, DXF, Chrome
→
Photo-
lithography
lithography
20nm-4µm
→
Nano-
imprinting
imprinting
UV & thermal NIL
→
Thin Film
Deposition
Deposition
PVD, CVD, ALD
→
Liftoff
Patterning
Patterning
Metal lift-off
→
Electro-
plating
plating
Cu, Ni, Au, Sn
→
Etching
DRIE, ICP-RIE, Wet
→
Annealing
N2/H2/vacuum/RTA
→
Ion
Implant
Implant
Si, SiC, GaN
→
CMP &
Grinding
Grinding
Planarization
→
Wafer
Cleaning
Cleaning
RCA · plasma · megasonic
→
Dicing &
Packaging
Packaging
Blade, laser, stealth
Bumping · Metallization · Quantum
UBM
Deposition
Deposition
Ti/Pt/Au · BLM
Gold
Bump
Bump
1-20 µm · TC/ACF
Indium
Bump
Bump
10µm pitch · FPA
AuGe / AuSi
Attach
Attach
356/363°C eutectic
High-Pb
C4
C4
95/5 · low-alpha
SLID / TLP
Stacks
Stacks
bond low, remelt high
Al-Ge
Sealing
Sealing
424°C frames
Ohmic
Contacts
Contacts
GaAs · GaN · RTA
Cryo & UHV
Metallization
Metallization
AuSn · seal rings
Optical
Access
Access
windows · meshes
MEMS Vapor
Cells
Cells
unfilled bodies
TFOI
Wafers
Wafers
quartz-on-Si · custom LNOI
Quantum
Technology
Technology
platform overview
Advanced Packaging & Integration
Wafer
Bonding
Bonding
Cu-Cu, Eutectic
→
TSV
Fabrication
Fabrication
High AR, Cu fill
→
TSV
Reveal
Reveal
Backgrind + CMP reveal
→
TGV
Fabrication
Fabrication
20 µm dia, panels
→
RDL
Fabrication
Fabrication
Fan-in, Fan-out
→
Packaging
& Assembly
& Assembly
Wire bond, flip-chip
→
3D/2.5D
Packaging
Packaging
TSV+RDL+UBM+C4
→
AuSn
Bump
Bump
PVD lift-off · fluxless
→
Biochip &
Microfluidics
Microfluidics
Glass · Si · polymer
→
SiPho
Packaging
Packaging
TSV · RDL · UBM · C4
Typical engagement models
How customers typically engage us
Single-process support
For customers with a defined flow who need one specific step such as DRIE, wafer bonding, plating, or dicing.
Multi-process prototyping
For R&D and proof-of-concept work requiring multiple coordinated fabrication steps under one project.
Advanced packaging builds
For TSV/TGV, redistribution, bonding, bumping, and wafer-level integration programs.
Pilot and low-volume production
For customers moving from early development toward repeatable manufacturing support.
What to send for feasibility review
Substrate material and size · Target process or sequence · Layer stack if known · Quantity · Target timeline · Drawings or design files if available (not required for first contact)
Ready to submit your specifications?
Our Technical Intake Portal guides you through each parameter step by step - select your process and the form adapts automatically.
Why it matters
The foundry, upgraded.
We have removed the friction from semiconductor fabrication. Precision engineering delivered with modern speed and full transparency.
| Feature | Traditional "Black Box" Foundry | Nanosystems JP Inc. - Modern Foundry |
|---|---|---|
| Onboarding | 3-6 months (NDAs, credit checks, legal) | 48 hours (digital NDA and engineer review) |
| Minimum order | Full lot (25+ wafers) | From 1-5 wafers for R&D |
| Communication | Account managers (sales-led) | Technical engineers, initial engineering response review |
| Process control | Rigid fixed menus | Customizable, optimized flows |
| Transparency | "Wait for the shipping notice" | Milestone updates from photolithography through to dicing |
Full Capabilities
Complete Fabrication Capabilities
At Nanosystems JP Inc., we offer a complete range of semiconductor, MEMS, and nano-fabrication processes - from substrate procurement through front-end processes, back-end integration, and final assembly to diced chip, managed under a single project.
| Process | Key Specifications | Substrate / Size |
|---|---|---|
| CORE SEMICONDUCTOR PROCESSES | ||
| Substrate & Wafer Supply | Si, Glass, SiC, GaN, GaAs, InP, InGaAs, Sapphire, Quartz, LiNbO₃ and more | 2″-12″ wafers · glass panels to 550×650mm |
| Design & Mask Fabrication | Chrome-on-glass, quartz masks. GDS/DXF input. DRC + fracturing. | Standard and large-format masks |
| Photolithography | E-beam 20 nm · KrF stepper · Large-format stepper 4 µm (500×600 mm) · Mask aligner · X-ray LIGA | Up to 12″ + panels to 500×600mm |
| Nanoimprinting (NIL) | UV NIL 50nm · Thermal NIL · Large format 500×500mm · Mold fabrication (Si/Ni/quartz) | Up to 500×500mm |
| Thin Film DepositionWafer Metallization & PVD | PVD (sputtering, e-beam, ion plating) · CVD (LPCVD, PECVD) · ALD · MBE · Roll-to-roll · 100+ materials | Up to 500×600mm |
| TFT & Display Backplane | IGZO TFT · BG-ES architecture · Multi-layer metal wiring (up to 4 layers) · P-CVD dielectrics · Organic ILD · 5 µm L/S photolithography | Glass substrate · 0.5-0.7 mm · 100×100 mm to 400×300 mm |
| Electroplating & Electroforming | Cu/Ni/Au/AuSn electroplating · TSV/TGV fill · LIGA Ni electroforming (1µm features) | Up to 300mm + large panels |
| EtchingDeep Silicon Etching (DRIE) | ICP-RIE (compound semi, SiC, waveguides) · RIE · DRIE (>50:1 AR, Bosch) · KOH/TMAH/BOE wet etch | Up to 12″ |
| Annealing | N₂ · H₂ · Vacuum · RTA ambient to 1200°C (1-400°C/s) · SiC high-temp anneal to 2000°C · 193 nm laser anneal · Furnace 350-1100°C · SiC carbon cap | Up to 12″ |
| Ion Implantation | B, P, As, BF₂, Al, N and 50+ more · 0.1 keV to 100 MeV incl. PIII · Hot implant to 600°C · Samples to 300 mm · RTA to 1800°C | Chips to 300mm |
| CMP & Wafer Grinding | Metal/insulator CMP · SiC/sapphire polishing · Pre-bonding CMP · Backgrinding to 50µm | Up to 12″ |
| Dicing | Blade and stealth laser dicing · tape and frame handling | Up to 300mm |
| ADVANCED PACKAGING | ||
| Wafer Bonding | Hybrid (±1µm) · Thermocompression · Eutectic (AuSn/AuGe) · Fusion · Anodic · Glass frit · PDMS | Chips to 12″ |
| TSV Fabrication | DRIE >100µm · Void-free Cu fill · Oxide liner (PE-TEOS/ALD) · Barrier/seed · CMP | Up to 12″ |
| TSV Reveal | Temporary bonding · Backgrinding · Dry etch reveal · SiN/SiO₂ deposition · CMP | Up to 12″ |
| TGV Fabrication | Via from 20µm · Aspect ratio 10:1 · SEM-verified fill · Cu fill · Double-sided RDL · BGV available | Wafers + panels to 510×510mm |
| RDL Fabrication | Polymer passivation (BCB/PBO/PI) + Cu damascene (single + double) · Double-sided TGV RDL | Up to 12″ |
| Packaging & Assembly | Die/wire/flip-chip bonding · BEOL · UBM (ENIG/ENEPIG) · C4 bumping (Cu/CuSn/AuSn) | Up to 12″ |
| AuSn Bump Services (PIC) | PVD multilayer + electroplating · 80/20 standard + custom · Ti/Ni/Au UBM · ENIG/ENEPIG | 4″-12″ incl. cavity wafers |
| SPECIALTY SERVICES | ||
| Biochip & Microfluidics SiPho Wafer-Level Packaging | Glass/Si/polymer chips · PDMS soft litho · Injection molding · Organ-on-chip · MEA | Glass to 500×600mm |
| BUMPING, METALLIZATION & QUANTUM | ||
| UBM Deposition | Ti/Pt/Au · Ti/Ni/Au · Cr-based BLM · one pump-down with in-situ clean | 4-12″ + pieces |
| Gold Bump Services | Electroplated and evaporated Au bumps 1-20 µm · TC / thermosonic / ACF ready | 4-12″ |
| Indium Bump Services | Evaporated In bumps to 10µm pitch · as-deposited flat-top · cold weld / TC ready | 4-12″ |
| AuSn Bump Services | 80/20 AuSn multilayer PVD and plating · fluxless eutectic 278°C | 4-12″ |
| AuGe & AuSi Die Attach | Stacked evaporation to eutectic ratio · 356°C / 363°C first-level attach | 4-12″ + backside |
| High-Pb Solder Bumps | 95Pb/5Sn · 97Pb/3Sn C4-class evaporated bumps · low-alpha Pb on request | 4-12″ |
| SLID / TLP Stacks | Cu/Sn · Au/In · Ag/In deposited couples · bond low, remelt high | 4-12″ |
| Al-Ge Wafer-Level Sealing | 424°C eutectic seal frames on matched wafer pairs | 4-12″ |
| Ohmic Contact Metallization | GaAs · GaN contact stacks · RTA alloying · TLM structures on request | 2-12″ |
| Cryo & UHV Metallization | Fluxless AuSn · Ti/Pd/Au · seal rings from ~20µm · AlN / SiC carriers | 4-12″ + carriers |
| Optical Access Components | Double-side patterned windows · apertures · ~1µm-class meshes · unfilled TGV holes | Wafers + chip-scale |
| MEMS Vapor Cells | DRIE cavity bodies · anodic / adhesive bonding · delivered unfilled | 4-12″ pairs |
| Thin-Film-on-Insulator | Quartz-on-Si below 570°C · custom LNOI · piezo films · 3-5 wafer lots | 4-6″ |
Development and evaluation services
Orderable deliverables for evaluation programs
Small-quantity deliverables for teams evaluating a process, a material, or an assembly route.
| Service | What it is | Delivery |
|---|---|---|
| Patterned test wafers | CMP and process evaluation substrates with your pattern and film stack | Full wafers or diced coupons; delivered at the agreed process stage |
| Glass TGV coupons | Hole-only, seeded, lined, or filled vias; routed prototypes | Wafer or coupon format; customer pre-drilled glass reviewed |
| Microchannel cooling structures | Etched channels, bonded flow structures, heater and sensor test chips | Open or bonded delivery; leak and pressure testing by agreement |
| Cu pillar and SnAg microbumps | Pillars with SnAg caps and SnAg solder bumps on your pad stack | As-plated or reflowed; bumped wafers or diced dies |
| Laser submounts and optical benches | Si and AlN submounts, V-grooves, patterned metal, AuSn-ready pads | Bare, metallized, or solder-coated components |
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will give an initial response within one business day. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.