TSV Fabrication Sequence: 5-Step Process
At Nanosystems JP Inc., we offer a complete 5-step TSV fabrication flow, DRIE Bosch etching at >50:1 aspect ratio, PECVD SiO₂ dielectric liner, ALD Al₂O₃ for conformal thin liners, TiN/Ta barrier and Cu seed by sputtering, void-free Cu electroplating, and CMP endpoint control. For 3D-IC memory stacking, 2.5D silicon interposers, and MEMS-on-CMOS integration.
Through-Silicon Vias are copper-filled vertical channels etched through the full silicon wafer thickness, providing electrical signal and power connections between stacked die layers in 3D-IC packages. Without TSV, dies in a stack must communicate via slow, power-hungry wire bonds around the edge of the stack. TSV enables the bandwidth density of HBM memory and the compact form factor of advanced sensor stacks.
At Nanosystems JP Inc., every step of the TSV flow, etching, lining, barrier, plating, and polishing , executed as a single continuous programme.
The DRIE Bosch process alternates between SF₆ plasma etch cycles (isotropic silicon removal) and C₄F₈ passivation cycles (depositing a fluoropolymer layer on sidewalls), producing near-vertical sidewalls with controlled Bosch scalloping below 100nm amplitude. The SiO₂ hard mask provides >100:1 etch selectivity over silicon, enabling deep vias (over 100µm) without mask erosion. Etch uniformity across the wafer is monitored by laser interferometry or optical emission spectroscopy for endpoint detection. Via diameter, depth, and sidewall angle are measured by cross-section SEM on monitor wafers before production lots proceed.
The exposed silicon sidewall and bottom are electrically isolated by a conformal dielectric layer. PECVD SiO₂ (PE-TEOS) is deposited at temperatures below 400°C to protect front-side devices , providing high step coverage into the deep via geometry. The dielectric must cover the complete via sidewall without pinholes or thinning at the corners, as any bare silicon exposure would create a leakage path. For vias requiring thinner, more conformal liners (narrow pitch or high-density TSV arrays), ALD Al₂O₃ provides angstrom-level thickness control and near-100% step coverage. The liner thickness is confirmed by cross-section TEM or ellipsometry on monitor wafers.
Copper is a fast diffuser in silicon, it reaches transistors at room temperature within hours of contact. A diffusion barrier is mandatory: TiN, Ta, TiW, or Ti is sputtered over the dielectric liner at conformal coverage into the via geometry. Immediately after the barrier, a thin Cu seed layer is sputtered , providing the electrically conductive nucleation surface needed for electroplating to initiate uniformly across the via bottom and sidewalls. Both barrier and seed layers require step coverage down the full via depth, even at >50:1 aspect ratios, achieved by ionised PVD (iPVD) or collimated sputtering conditions. Sheet resistance of the seed layer is measured by 4-point probe before plating.
Copper electroplating using bottom-up superfill chemistry, a combination of accelerator, suppressor, and leveller additives in the electrolyte, preferentially deposits Cu from the bottom of the via upward, preventing the void formation that would result from top-down fill. The plating current density is carefully controlled to avoid Cu mounds or dimples at the via center. After plating, wafers are annealed at approximately 400°C under N₂ atmosphere, this drives Cu grain growth and relaxes the compressive stress built up during plating, significantly reducing wafer bow. Void-free fill is confirmed by cross-section SEM on representative vias across the wafer diameter before proceeding to CMP.
Cu CMP removes the electroplated overburden and planarises the wafer surface, stopping precisely on the barrier layer using eddy current in-situ endpoint detection on the Cu within the vias, or optical endpoint by reflectometry. The barrier layer is then cleared by a brief over-polish or second CMP step. The final surface presents Cu via tops flush with the surrounding SiO₂ or barrier , with a topography step of less than 5nm, ready for RDL dielectric deposition or direct wafer bonding. Post-CMP metrology: wafer bow (warpage), within-wafer Cu dishing, SiO₂ erosion, and surface roughness (Ra) are measured and reported in the process data sheet delivered to the customer.
TSV fabrication is never the only step. It fits into a larger flow, preceded by wafer-level device processing and followed by reveal, RDL, and bumping. All these steps are available as a single programme.
At Nanosystems JP Inc., we offer TSV fabrication as a complete programme , from DRIE etch through to CMP planarization. Via-first, via-middle, and via-last integration are all supported. The programme is managed end-to-end as one project, with direct technical engagement from inquiry through to delivery.
TSVs etched and filled before transistor fabrication begins. Enables the highest via density (tightest pitch) because the TSV fill anneal can be run at high temperature without damaging completed devices. However, the TSV must survive all subsequent CMOS thermal cycles.
TSVs fabricated after the transistors but before the metal interconnect layers. The most common approach for memory dies and mixed-signal ICs. Thermal budget is constrained by completed transistors, TSV anneal typically limited to 400°C.
TSVs etched and filled after all BEOL metal layers are complete. Maximum design flexibility, via position not constrained by front-end layout. Thermal budget most constrained (<300°C) due to completed Cu BEOL. Most common for interposer and MEMS-on-CMOS.
| Parameter | Specification / Range | Notes |
|---|---|---|
| Via Etch Method | DRIE, Bosch process | SF₆/C₄F₈ alternating cycles |
| Aspect Ratio (depth:width) | >>50:1 | Depth >100µm, width from ~3µm |
| Via Depth | Up to >100µm | Through-wafer or blind via |
| Sidewall Angle | 89–90° (near vertical) | Bosch scalloping <100nm amplitude |
| Hard Mask | SiO₂ | >100:1 selectivity over Si |
| Dielectric Liner, Standard | PECVD SiO₂ (PE-TEOS) | High step coverage, <400°C |
| Dielectric Liner, Conformal | ALD Al₂O₃ | Near-100% step coverage, narrow vias |
| Diffusion Barrier | TiN, Ta, TiW, Ti | Prevents Cu diffusion into Si/oxide |
| Cu Seed Layer | Sputter PVD | Ionised PVD / collimated for deep vias |
| Cu Fill Method | Electroplating, superfill | Bottom-up fill, additive chemistry |
| Fill Quality | Void-free | Confirmed by cross-section SEM |
| Post-Plate Anneal | ~400°C, N₂ atmosphere | Grain stabilisation, stress relief |
| CMP Endpoint | Eddy current / optical | Stops on barrier layer |
| Post-CMP Topography | <5nm step height | Dishing and erosion measured |
| Wafer Size | 2 inch to 12 inch (300mm) | All standard wafer diameters |
| Via Integration Timing | Via-first, via-middle, via-last | Process flow dependent |
High-bandwidth memory (HBM) uses TSV arrays to connect stacked DRAM layers to each other and to the logic die beneath. Each HBM2/HBM3 die contains thousands of TSVs at fine pitch. The bandwidth increase over conventional DRAM is directly enabled by the parallel via array, something bond wires cannot achieve.
A silicon interposer die contains a TSV array connecting chiplets on the front surface to C4 solder bumps on the back. The interposer routes signals between CPU, HBM, and I/O chiplets at much finer pitch than an organic package substrate, enabling chiplet integration for HPC and AI accelerator packages.
MEMS inertial sensors (accelerometers, gyroscopes) stacked face-to-face on CMOS readout dies using TSV for vertical signal routing. Eliminates bond wire parasitic inductance, critical for MEMS sensors operating above 1MHz. Enables the compact form factor needed for IMUs in drones, AR/VR headsets, and autonomous vehicles.
Silicon photonics interposers for co-packaged optics use TSVs to route electrical signals from the electronic IC to the photonic IC, and from both to the package substrate. TSV provides the electrical feedthrough while optical signals travel in-plane through waveguides. Critical for 800G/1.6T optical transceivers.
BSI image sensors use TSVs to connect the front-side CMOS readout circuit to the backside-illuminated pixel array, and then to the package substrate. The TSV enables a compact BSI architecture without wire bonds around the die edge. Applied in smartphone cameras, scientific sensors, and LiDAR receivers.
Coaxial TSV structures for RF MEMS and millimetre-wave packaging, a central signal via surrounded by grounded shield vias, providing high-isolation RF signal routing through the silicon substrate. Applied in 5G/6G front-end module integration and mmWave radar chips for automotive ADAS.
DRIE etch, PECVD/ALD liner, barrier/seed sputtering, Cu electroplating, and CMP are performed at the same coordinated project. No wafer shipping between steps, eliminating the contamination and surface degradation that happens when vias are exposed between process steps.
Most MEMS-scale foundries cap DRIE aspect ratios at 20:1 or 25:1. Our >50:1+ capability enables through-wafer TSVs in thicker substrates without requiring extreme wafer thinning, reducing process complexity and wafer fragility in thin-wafer handling.
Every production lot includes SEM cross-section inspection of representative vias after plating, before the wafer proceeds to CMP. Voids caught at this stage save the cost of CMP, TSV reveal, RDL, and bumping steps on a defective wafer. Not all TSV foundries include this inspection step.
TSV fabrication is rarely the final step, it is followed by TSV reveal (backgrinding + etch + passivation + CMP) and then RDL and bumping. All three phases are available and managed as one project, with no re-quoting, no technology transfer, and no scheduling complexity.
We handle all three TSV integration timing approaches, matching our process conditions to the thermal budget available at each stage of your device flow. Via-last at <300°C for completed BEOL wafers; via-middle at <400°C for post-transistor wafers; via-first at higher temperatures for blank substrates.
Run a single engineering wafer to optimize via depth, fill quality, liner integrity, and CMP endpoint before committing to a full production lot. The same process recipe scales to production without re-qualification, your prototype data is your production baseline.
Our complete 2.5D/3D interposer packaging flow covers TSV, TGV, RDL, and hybrid bonding - all managed as one project at Nanosystems JP Inc. No inter-vendor wafer transfers.
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.
