TSV (Through Silicon Vias) for 3D Staking/ 2.5D Interposers

At Nanosystems JP, we provide TSV fabrication services, a process that involves creating electrical connections between layers of a semiconductor device to create high-density, high-performance integrated circuits.

Typical steps, fabrication techniques & key points:

1. High aspect ratio etching using DRIE (Deep reactive dry etching)

   • Over 100um deep

   • SiO2 hard mask

   • BOSCH process

   • Smooth (small sidewall scalloping), Uniform, vertical side wall profile

2. Oxide deposition / Dielectric liner

   • High step coverage

   • Low-temperature growth

   • Low K dielectric

   • Low leakage current

   • PE-TEOS, SiO2 PECVD, Al2O3 ALD (Atomic layer deposition)

3. Barrier & seed layer deposition

   • Prevent diffusion of metal into oxide

   • High step coverage

   • Diffusion barrier

   • TiN, Ta, SiN,TiN, TiW, Ti

   • Based on electroplating Cu, Tungsten, etc., seed layer deposition by sputtering

4. Plating & Annealing

   • Void free

   • Low stress to avoid warpage

   • Typical material Cu, Tungsten

   • No Cu mounds defects

   • Annealing at ~400C.

5. CMP

   • Endpoint control

If you have any questions about our TSV fabrication process, please don't hesitate to contact us.

We look forward to helping you create the perfect integrated circuit for your application.