Silicon photonic integrated circuits combine multiple optical functions, waveguiding, modulation, detection, and coupling, on a single Si chip. Fabricating and packaging these devices requires a sequence of precision steps that we provide end-to-end.
SOI Substrate & Waveguide Patterning
Silicon-on-insulator (SOI) wafers provide the high-index Si waveguide core on a buried SiO₂ cladding. KrF stepper (50nm resolution) patterns the waveguide layer, the most critical lithography step in SiPho fabrication. ICP-RIE etches the Si waveguide to depth while maintaining sidewall smoothness below 2nm RMS. Sidewall roughness directly controls propagation loss, our ICP-RIE achieves <2 dB/cm loss on standard SOI platforms.
Nanoscale Grating & Coupler Structures
Grating couplers, photonic crystal structures, and sub-wavelength anti-reflection gratings require feature sizes below 100nm, requiring e-beam lithography. E-beam direct-write from GDS file without mask cost, enabling rapid design iteration on sub-100nm SiPho features. For volume production, e-beam master + UV-NIL replication produces sub-wavelength gratings at lower cost. Apodised grating couplers for <1 dB fibre-chip coupling loss.
III-V Laser Integration - AuSn Bump Fabrication
Silicon cannot generate light - InP or GaAs laser diodes must be flip-chip bonded onto the SiPho PIC. We fabricate the wafer-level AuSn bumps (80/20 eutectic, PVD multi-layer + lift-off) that make this bonding possible: fluxless, hermetic, with self-aligning surface tension that places the laser facet within ±1µm of the Si waveguide input. Bumped wafers are delivered ready for flip-chip assembly at your facility or assembly partner.
TSV & TGV, SiPho Interposer
Silicon or glass interposers with TSV/TGV provide electrical connections between the SiPho PIC, electronic IC (EIC), and package substrate. Our DRIE TSV (50:1 aspect ratio) and TGV (up to 510×510mm glass) enable the vertical signal routing in co-packaged optics modules for 400G/800G/1.6T optical transceivers. Cu damascene RDL routes signals between chiplets at sub-2µm line/space.
Thin Film Deposition Optical Layers
Optical cladding and functional thin films on SiPho devices: PECVD SiO₂ and SiN as upper cladding, ALD Al₂O₃ for passivation, sputtered SiO₂ for planarization before upper cladding deposition. TiO₂ and Ta₂O₅ for high-refractive-index waveguides. Ge deposition for photodetector regions. PZT piezoelectric thin film for electro-optic modulators. All deposition processes calibrated for optical quality, refractive index and loss are characterized post-deposition.
Stealth Dicing, Clean Waveguide Facets
Standard blade dicing floods the wafer with water at high pressure, water at the waveguide facet causes permanent coupling loss and photoresist contamination of optical surfaces. Stealth laser dicing is the only method that produces clean dry waveguide facets. The laser modifies only the silicon interior; water never contacts the surface. Direct use after dicing, no facet polishing required for many applications.