Packaging for 3D/2.5D IC — TSV, TGV, RDL, UBM, C4

3D-IC and 2.5D Integration

Stacking dies vertically and tiling
chiplets side-by-side

3D-IC stacks dies vertically connected by TSV, achieving the highest bandwidth density (HBM) and shortest inter-die distance. 2.5D places chiplets side-by-side on a common interposer, enabling heterogeneous integration of dies from different foundries and nodes. Both approaches are available at Nanosystems JP Inc.

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3D-IC, Vertical Stacking

Dies stacked face-to-face or face-to-back and connected by TSV arrays, the architecture of High-Bandwidth Memory (HBM). TSV provides vertical electrical connections with sub-10µm pitch, enabling bandwidth density 10–100× higher than package-level wire bonding or flip-chip on organic substrate. Each die in the stack requires TSV fabrication, reveal, and micro-bump formation before stacking.

TSV arrays at die pitch Micro-bumps between layers HBM2/HBM3 architecture 10–100× bandwidth vs wire bond Face-to-face or face-to-back

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2.5D, Chiplet Integration on Interposer

Multiple chiplets (CPU, HBM, I/O, analog) placed side-by-side on a silicon or glass interposer. The interposer provides high-density RDL routing between chiplets at finer pitch than an organic package substrate can achieve. TSV or TGV in the interposer connects front-side chiplets to back-side C4 bumps for bonding to the organic package substrate. Enables heterogeneous integration of dies from different foundries.

Si or glass interposer Fine-pitch RDL routing Heterogeneous chiplets Different foundries/nodes CoWoS · EMIB · SoIC

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Why a Single-Point Integration Flow Matters

A typical 3D/2.5D integration process involves multiple sequential steps, often distributed across different facilities. This introduces repeated wafer transfers, increasing the risk of contamination, surface degradation, handling damage (especially for thin wafers), and schedule delays. A delay at any one step can cascade and impact the entire project timeline.

At Nanosystems JP Inc. we provide a single-point integration approach, managing the full process flow from start to finish. All steps are coordinated under a unified framework, ensuring consistency and continuity throughout the project.

Minimized transfer risk through tightly controlled process flow
Consistent process management across all steps
Continuous data tracking with no information gaps
One schedule, one project

This approach ensures higher reliability, better communication, and smooth execution - especially for complex prototyping projects.

Zero inter-vendor transfers No contamination risk Continuous process data One schedule, one contact

Seven-Step Integration Flow

From blank silicon or glass
to bumped, assembly-ready interposer

Each step builds directly on the previous, and the quality of each step determines the yield of all subsequent steps.

Key Integration Technologies - 3D silicon interposer with Through-Silicon Vias (TSV), Redistribution Layer (RDL), micro-bumps and copper routing layers

1

TSV Fabrication

Through-Silicon Via fabrication using DRIE Bosch process: 50:1 aspect ratio, over 100µm depth. Five sub-steps: SiO₂ hard mask DRIE etch, PECVD SiO₂ or ALD Al₂O₃ dielectric liner, TiN/Ta barrier and Cu seed sputtering, void-free Cu electroplating with superfill additive chemistry, and CMP endpoint-controlled planarization. All five steps , sequenced without inter-step wafer exposure. Void-free fill verified by cross-section SEM before CMP. Via-first, via-middle, or via-last timing supported depending on device architecture and thermal budget.

DRIE Bosch 50:1 >100µm depth PECVD SiO₂ + ALD Al₂O₃ TiN/Ta barrier + Cu seed Void-free Cu fill (SEM verified) CMP endpoint control

2

TGV Fabrication (Glass Interposer Option)

For applications requiring lower dielectric loss than silicon, RF front-end modules, optical interposers, glass interposers with Through-Glass Vias (TGV) provide a superior substrate. Our TGV capability supports borosilicate and aluminosilicate glass substrates up to 510×510mm, the largest TGV panel format available at any foundry globally. Cu-filled TGV using laser drilling, wet etch, and electroplating provides vertical electrical connections through the glass. Customers choose between Si (TSV) and glass (TGV) interposers based on their dielectric loss requirement, CTE compatibility, and cost target, both available .

510×510mm panel, largest available Borosilicate + aluminosilicate Laser drill + wet etch + Cu fill Lower dielectric loss than Si RF · Optical · Low-loss applications

3

TSV / TGV Reveal

After TSV fabrication, the wafer is bonded face-down to a temporary carrier using releasable adhesive. Backside grinding reduces wafer thickness to 50–100µm, approaching the Cu via tips from below. A controlled SF₆ plasma etch removes the remaining thin Si skin and exposes the Cu tips precisely, endpoint by Optical Emission Spectroscopy (OES), stopping within 1–2µm of the Cu surface without Cu damage. PECVD SiN/SiO₂ passivation is deposited conformally over the exposed backside. CMP removes passivation from the Cu tops, leaving clean Cu contacts flush with the dielectric, ready for RDL lithography.

Temporary carrier bonding Backgrind to 50–100µm SiN/SiO₂ passivation CMP, Cu contacts exposed no inter-vendor transfer

4

RDL Fabrication

Redistribution layers reroute the TSV/TGV contacts from via pitch to bump pitch, and provide the lateral signal routing between chiplet landing pads on the interposer front surface. Two routes available: polymer passivation RDL (BCB, PBO, or polyimide, lower cost, lower temperature) and Cu damascene RDL (sub-2µm line/space for high-density chiplet-to-chiplet routing). Multi-layer RDL (1–6 layers) builds the routing complexity required for CPU-to-HBM signal interconnects on a 2.5D silicon interposer. RDL begins immediately after reveal CMP, while the Cu contact surface is fresh.

BCB · PBO · Polyimide polymer RDL Cu damascene sub-2µm L/S 1–6 RDL layers Immediate after reveal CMP Fan-in WLCSP or fan-out FOWLP

5

Polyimide Film Interposer (2.5D Alternative)

For applications where a rigid silicon or glass interposer is over-engineered or too expensive, a thin polyimide film interposer with Cu-patterned RDL provides a flexible, low-cost 2.5D integration option. PI film interposers are particularly suited to mid-tier HPC and networking ASICs where chiplet I/O density is moderate (5–20µm L/S RDL sufficient) and where the flexibility of the PI film enables non-planar assembly configurations. We fabricate PI film interposers , Cu plating, RDL lithography, and via formation on PI substrate.

Polyimide film substrate Cu RDL on PI Flexible, non-planar assembly Lower cost than Si interposer Mid-tier HPC · Networking ASICs

6

UBM, Under Bump Metallisation

Under Bump Metallisation prepares the RDL pads for solder bumping. Two UBM options: ENIG (Electroless Nickel Immersion Gold) deposits a Ni diffusion barrier (~3–5µm) topped with a thin Au flash (~0.05–0.1µm) that prevents Ni oxidation and provides Au-Sn wetting during reflow. ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) adds a Pd interlayer between Ni and Au, providing superior bond strength for both solder and Au wire bonding. The Pd layer prevents the brittle Ni₃Sn₄ intermetallic formation that causes embrittlement failure in ENIG joints under thermal cycling.

ENIG, Ni(3–5µm) + Au flash ENEPIG, Ni + Pd + Au Pd prevents Ni₃Sn₄ embrittlement Compatible with Au wire bond Electroless, no photomask needed

7

C4 Solder Bumping & Chiplet Flip-Chip

C4 (Controlled Collapse Chip Connection) SnAg solder bumps are formed by electroplating through a photoresist mask on the UBM pads. Solder volume is controlled by the photoresist opening geometry and plating time, determining final collapsed bump height after reflow. During reflow above the SnAg liquidus (217–221°C), molten solder self-aligns to the UBM pad by surface tension, correcting placement offsets from the pick-and-place step. Chiplets (CPU, HBM base die, I/O die) are flip-chip bonded to the interposer in the same coordinated project immediately after bumping, completing the 2.5D integration without further wafer transfer. Carrier wafer debond follows after the chiplet assembly step is complete.

C4 SnAg electroplating Self-aligning reflow 217–221°C Chiplet flip-chip immediate after bump Carrier debond after assembly X-ray void inspection post-reflow Daisy chain electrical test

Fabrication Process

Typical Process Flow
End-to-end 3D/2.5D IC integration

From TSV formation through backside processing, RDL, bumping, die bonding, and final encapsulation - each step is managed as one project at Nanosystems JP Inc.

1

TSV Fabrication

Through-Silicon Vias etched by DRIE (50:1 aspect ratio) and filled with Cu via barrier/seed + electroplating to create vertical electrical connections through the silicon wafer.

Silicon

Cu Fill

SiO₂ Liner

2

Backside Processing

Wafer thinning, TSV reveal via CMP, backside RDL patterning, and UBM/C4 bump formation for bottom-side connectivity.

2.1

TSV Reveal

Wafer thinning + CMP to expose Cu TSV tips from the backside

2.2

Backside RDL

Redistribution layer for fan-out routing on backside

2.3

UBM & C4 Bumping

Under-bump metallization and solder bump formation for flip-chip attach

Silicon

Cu

Dielectric/RDL

UBM

Solder

3

Frontside Processing

Frontside RDL routing, UBM deposition, and Cu pillar fabrication for top-side die-to-die or die-to-interposer interconnection.

3.1

Frontside RDL

Multi-layer redistribution for signal fan-out on active side - <2µm line/space in Cu damascene

3.2

UBM & Cu Pillar Fabrication

Copper posts with solder caps for fine-pitch die-to-die or die-to-interposer interconnect

Silicon

Cu

Dielectric/RDL

UBM

Solder Cap

4

Chip / Wafer Bonding & Stacking

Die or wafer-level bonding to attach top die(s) onto the interposer or bottom die, with precise alignment of microbumps or hybrid bond pads. Supports Cu-Cu hybrid, eutectic, fusion, and SAB bonding.

Logic Die

HBM Die

Interposer

Microbumps

Cu TSV

5

Package Substrate Attach

The assembled die stack is flip-chip bonded onto an organic package substrate via C4 solder bumps, providing I/O routing to the board level.

Package Substrate

Interposer

C4/Microbumps

BGA Balls

6

Underfill & Molding

Capillary underfill strengthens solder joints and absorbs CTE mismatch stress. Mold compound encapsulates the die stack for mechanical protection and environmental reliability.

Mold Compound

Underfill

Package Substrate

BGA Balls

Interposer Options

Silicon, glass, or polyimide matched to your performance and cost target

The interposer substrate determines dielectric loss, CTE match to the chiplets, RDL density capability, and cost. All three interposer types are available .

Silicon Interposer (TSV)

HIGHEST RDL DENSITY · STANDARD APPROACH

The dominant 2.5D interposer substrate, used in CoWoS (TSMC), Foveros (Intel), and similar advanced packaging platforms. Silicon enables the finest RDL line/space (<2µm Cu damascene) and TSV pitch compatible with high-bandwidth memory footprints. CTE close to chiplet silicon minimizes thermomechanical stress during temperature cycling.

RDL min L/S<2µm (Cu damascene)

Via typeTSV, DRIE 50:1

Dielectric constant~11.7 (Si)

Max sizeUp to 12 inch (300mm)

CTE (Si)2.6 ppm/°C, matches chiplets

Best forHPC · AI · HBM-on-Logic · Highest density

Glass Interposer (TGV)

510×510mm PANEL · LOWEST DIELECTRIC LOSS

Glass interposers offer lower dielectric constant and loss tangent than silicon, making them superior for RF and optical applications where signal integrity at 10–100+ GHz determines system performance. Our 510×510mm panel-format TGV capability is unique globally, enabling far more interposers per panel run than wafer-format competitors and dramatically reducing cost-per-interposer at volume.

RDL min L/S~5µm (polymer) / ~2µm (damascene)

Via typeTGV, laser + Cu fill

Dielectric constant~4–6 (borosilicate)

Max panel size510×510mm, largest globally

CTE (borosilicate)3.2 ppm/°C

Best forRF · 5G/6G · Optical · Low-loss

Polyimide Film Interposer

FLEXIBLE · LOW COST · 2.5D ALTERNATIVE

Thin polyimide film with Cu-patterned RDL provides a flexible, low-cost alternative to rigid silicon or glass interposers. PI film interposers enable non-planar assembly configurations not possible with rigid substrates, wrapping around curved surfaces, flexing during thermal cycling without stress concentration. Fabricated using roll-to-roll or sheet lithography, Cu plating, RDL patterning, and via formation on PI substrate, .

RDL min L/S~5–10µm

Via typeLaser via + Cu fill

FlexibilityYes, non-planar assembly

CostLowest of three options

Best forMid-tier · Networking · Flexible modules

Integration Specifications

Complete 3D/2.5D IC packaging
parameters

Step / Technology	Specification	Notes
TSV Etch	DRIE Bosch: 50:1 aspect ratio, >100µm depth	SiO₂ hard mask; Bosch scalloping <100nm
TSV Liner	PECVD SiO₂ or ALD Al₂O₃	<400°C; high step coverage; pinhole-free
TSV Barrier/Seed	TiN/Ta barrier + Cu seed by sputtering	High step coverage; 4-point probe QC
TSV Cu Fill	Superfill electroplating, void-free	SEM cross-section verified; anneal ~400°C N₂
TSV CMP	Endpoint on barrier; topography <5nm	Eddy current endpoint; dishing/erosion measured
TGV Panel Size	Up to 510×510mm	Borosilicate and aluminosilicate glass
TGV Via Fill	Laser drill + wet etch + Cu electroplating	Cu-filled TGV for electrical connections
TSV/TGV Reveal	Carrier bond → backgrind → OES etch → passivation → CMP	50–100µm final thickness; ±2µm uniformity
Reveal Endpoint	OES on Si/Cu interface, stops within 1–2µm of Cu	Cu protrusion measured by profilometry
RDL, Polymer	BCB (k=2.65), PBO (k=2.9), Polyimide (k=3.2–3.5)	Photosensitive BCB/PBO for low-cost patterning
RDL, Cu Damascene	Single and double damascene; <2µm line/space	CVD SiO₂ or low-k; superfill Cu + CMP
RDL Metal Layers	1–6 layers	Fan-in WLCSP or fan-out FOWLP
PI Film Interposer	Flexible polyimide; Cu RDL; laser via	~5–10µm min L/S; non-planar assembly
UBM, ENIG	Electroless Ni (3–5µm) + Au flash (0.05–0.1µm)	Solder wetting + Ni diffusion barrier
UBM, ENEPIG	Electroless Ni + Pd (0.05–0.2µm) + Au	Superior to ENIG for thermal cycling reliability
C4 Bumping	SnAg electroplating; self-aligning reflow 217–221°C	Pitch from 150µm; X-ray void inspection
Chiplet Flip-Chip	Thermocompression or reflow; ±2µm placement	CPU/HBM/I/O chiplets to interposer
Carrier Debond	Thermal, UV, or mechanical release	After chiplet assembly; controlled conditions
Wafer/Panel Size	TSV: 2–12 inch; TGV: up to 510×510mm	All standard diameters + panel format

Applications

3D/2.5D integration across
every advanced semiconductor platform

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AI Accelerator HBM Stacking

HBM2/HBM3 memory stacked on AI accelerator logic using TSV and µ-bump arrays. High-bandwidth memory delivers the memory bandwidth that GPU and TPU compute engines require. Each HBM stack (4–12 DRAM dies) is assembled using TSV reveal, µ-bump formation, and thermocompression bonding, then flip-chip bonded to the logic interposer.

TSV reveal → µ-bump → TC bond → 2.5D interposer · HBM2/HBM3 · AI/GPU/TPU

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HPC Chiplet Packages

CPU, HBM, I/O, and analog chiplets from different foundries integrated on a silicon or glass 2.5D interposer. Fine-pitch Cu damascene RDL routes signals between chiplets at densities an organic substrate cannot support. Used in data centre processors, high-performance computing nodes, and network switch ASICs.

Si interposer · Cu damascene <2µm · CPU + HBM + I/O · CoWoS-like

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Silicon Photonics Co-Packaging

SiPho PIC chiplet and electronic IC chiplet co-integrated on glass or silicon interposer. TGV glass provides low dielectric loss for RF signals at 100+ GHz alongside optical waveguide routing in-plane. AuSn flip-chip of laser sources onto the PIC. C4 bumping of the full assembly to package substrate.

TGV glass interposer · SiPho + EIC chiplets · AuSn laser flip-chip · 400G–1.6T

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MEMS-on-CMOS Stacking

MEMS sensing die (accelerometer, gyroscope, pressure sensor) stacked face-to-face on CMOS readout IC using TSV. Eliminates bond wire parasitics critical for >1MHz MEMS operation. Enables WLCSP packaging of the full MEMS+CMOS stack at wafer level, achieving IMU package dimensions impossible with wire-bonded approaches.

TSV · MEMS + CMOS face-to-face · WLCSP · IMU · Drones · AR/VR

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RF Front-End (Glass Interposer)

GaN/GaAs RF chiplets integrated on TGV glass interposer for 5G/6G front-end modules. Glass substrate provides the low dielectric loss tangent at mmWave frequencies that silicon interposer cannot match. Panel-format TGV (510×510mm) enables cost-effective high-volume production of RF module interposers.

TGV glass 510×510mm · GaN/GaAs RF chiplets · 5G/6G mmWave FEM

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Power Chiplet Integration

SiC and GaN power chiplets integrated on interposer with double-sided contacts via TSV, enabling top-and-bottom cooling in 3D power modules for EV traction inverters. TSV reveal provides the backside metal contacts; RDL routes gate and source signals; C4 bumping connects to the power module substrate.

TSV double-sided · SiC/GaN · Top+bottom cooling · EV inverter · Power module

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BSI Image Sensor Stacking

Backside-illuminated image sensor pixel die stacked on CMOS readout die using TSV, the architecture of all modern smartphone cameras. TSV reveal exposes backside contacts for C4 bumping to carrier substrate. Wafer-level packaging eliminates bond wires and achieves minimum optical sensor footprint.

TSV reveal · BSI pixel + CMOS readout · C4 to substrate · Smartphone · LiDAR

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Network Switch ASICs

High-radix network switch chiplets with integrated HBM stacks on 2.5D silicon interposers, enabling 400G/800G Ethernet switching fabric in data centre switches. Cu damascene RDL on the interposer routes SerDes lanes between switch ASIC and I/O chiplets at multi-terabit/s aggregate bandwidth.

Si interposer · Switch ASIC + HBM + I/O · Cu damascene · 400G/800G Ethernet

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Space & High-Reliability 3D

Radiation-tolerant 3D-IC stacks for space applications, rad-hard logic die stacked on radiation-shielded DRAM using TSV. TSV eliminates bond wire inductance that causes signal integrity degradation in radiation-induced latch-up events. Full lot traceability from via etch through chiplet assembly.

TSV rad-hard stack · Radiation-tolerant dies · Lot traceability · Space-grade

Nanosystems JP Inc. - 3D/2.5D Capability

What makes our 3D/2.5D IC
packaging capability different

01

All 7 steps, one project

At Nanosystems JP Inc. we offer TSV fabrication, TGV fabrication, TSV/TGV reveal, RDL, polyimide film interposer, UBM, and C4 bumping with chiplet flip-chip assembly - all managed as one project with continuous process data flow.

02

Largest TGV panel: 510×510mm

Our TGV capability supports glass interposers for RF, optical, and cost-sensitive applications on panels up to 510×510mm - significantly larger than standard wafer formats - which reduces cost-per-interposer compared to wafer-scale processing.

03

Si and glass interposer, both available

At Nanosystems JP Inc. we fabricate both silicon (TSV) and glass (TGV) interposers. Customers choose the substrate based on their dielectric loss requirement, RDL density, and cost target without changing foundry. Most 3D packaging foundries offer one interposer substrate only.

04

Sub-2µm RDL for chiplet routing

Cu damascene RDL achieving sub-2µm line/space, the density required for CPU-to-HBM signal routing on a 2.5D silicon interposer. Not achievable with polymer RDL approaches available at standard packaging foundries. Essential for the bandwidth density that differentiates advanced chiplet packages from conventional multi-chip modules.

05

Inspection at every step

TSV SEM, grinding depth, passivation coverage, RDL thickness, UBM coverage, and C4 void percentage, all inspected with data reported to the customer before the next step. No yield surprises at final chiplet assembly after seven process steps have been completed on a defective wafer.

06

From 1 wafer prototype

Run 1–5 engineering wafers through the full 7-step flow to validate via depth, fill quality, reveal endpoint, RDL thickness, UBM coverage, and bump height before committing to production volumes. The same process recipe scales to production, no re-qualification required, no technology transfer to a production line.

Full packaging service

Packaging & Assembly: Beyond 3D/2.5D integration, our full packaging service covers backgrinding, dicing, die bonding, wire bonding, and flip-chip, every assembly step .

Packaging & Assembly →

Packaging for3D/2.5D IC Integration

3D-IC, Vertical Stacking

2.5D, Chiplet Integration on Interposer

Why a Single-Point Integration Flow Matters

TSV Fabrication

TGV Fabrication (Glass Interposer Option)

TSV / TGV Reveal

RDL Fabrication

Polyimide Film Interposer (2.5D Alternative)

UBM, Under Bump Metallisation

C4 Solder Bumping & Chiplet Flip-Chip

TSV Fabrication

Backside Processing

TSV Reveal

Backside RDL

UBM & C4 Bumping

Frontside Processing

Frontside RDL

UBM & Cu Pillar Fabrication

Chip / Wafer Bonding & Stacking

Package Substrate Attach

Underfill & Molding

Silicon Interposer (TSV)

Glass Interposer (TGV)

Polyimide Film Interposer

AI Accelerator HBM Stacking

HPC Chiplet Packages

Silicon Photonics Co-Packaging

MEMS-on-CMOS Stacking

RF Front-End (Glass Interposer)

Power Chiplet Integration

BSI Image Sensor Stacking

Network Switch ASICs

Space & High-Reliability 3D

All 7 steps, one project

Largest TGV panel: 510×510mm

Si and glass interposer, both available

Sub-2µm RDL for chiplet routing

Inspection at every step

From 1 wafer prototype

Start your project. Response within 1 business day.

Packaging for
3D/2.5D IC Integration

Start your project.
Response within 1 business day.