Core Semiconductor Processes : Step 11 of 11

Wafer
Dicing Services

At Nanosystems JP Inc., we offer four dicing methods for every material, die shape, and substrate format. Stealth laser dicing, dry, no water, no dust, no chipping, for silicon photonics PICs and fragile MEMS. Blade dicing for standard Si/glass 4–12 inch. Large-format glass to 500×600mm. Diamond scribing for SiC/AlN/InP. Polygon dies (hexagon, octagon). Inspection, sorting, tray packing.

Standard blade Si/glass 4–12″Large glass 300×400 / 500×600mmStealth laser, dry, no dustDiamond scribing SiC/AlN/InPPolygon dies hex/octagonSiPho wafer dicingMetals Cu/SUS/AlInspection · Sorting · Tray pack
4
Dicing methods
500×600mm
Max glass panel
Polygon
Hex & octagon dies
Dry process
Stealth, no water, no chipping
Four Dicing Methods
Choose by material, die shape, and quality requirement

Each dicing method has distinct advantages for different substrate materials, die sizes, and cleanliness requirements. Our engineers recommend the optimal method based on your device.

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Standard Blade Dicing, Silicon

Rotating diamond blade dicing for silicon wafers from 4 to 12 inches. The workhorse of MEMS and IC singulation for rectangular dies on standard circular substrates. Automatic wafer map reading enables die-level quality sorting, accepted and rejected dies identified before dicing begins. Kerf width controlled to ±2µm for maximum die yield from expensive wafers. Cooling water spray prevents blade overheating and removes silicon swarf during cutting.

4–12 inch SiRectangular diesWafer map auto-read±2µm kerf controlCooling water spray
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Blade Dicing, Glass & Ceramic

Glass dicing for circular wafers (4–12 inch) and large rectangular panels up to 500×600mm. Quartz, borosilicate, aluminosilicate, and alumina (Al₂O₃) diced with glass-specific blades at lower feed rates than silicon. Thick glass dicing available for glass interposer substrates and MEMS package lids. Large-format glass dicing (300×400mm and 500×600mm) for display substrates, biochip arrays, and panel-level packaging, unique capability not available at standard dicing houses.

4–12 inch glass500×600mm panelsQuartz · Alumina · BorosilicateGlass-specific bladesBiochip · Interposer · Display

Stealth Laser Dicing

A pulsed laser modifies a plane inside the silicon wafer along the dicing streets without breaking the surface or producing any debris. A subsequent tape expand step singulates the dies, completely dry, no water, no dicing debris, no blade contact. Stealth dicing is the only method that preserves optical waveguide facet quality and protects fragile MEMS membranes from water and particle contamination during dicing. Enables polygon-shaped dies (hexagonal, octagonal) impossible with straight-blade dicing. No change in die size limitation, works from sub-millimetre dies to large multi-centimetre dies.

Dry, no waterNo dust or debrisNo chippingPolygon dies (hex/oct)SiPho waveguide facets protected
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Diamond Scribing

Mechanical scribing with a diamond tip along the dicing street followed by controlled cleaving, the standard singulation method for brittle compound semiconductors that chip or crack under blade dicing contact. SiC, AlN, and InP each have preferential crystallographic cleavage planes that guide the cleave, producing cleaner die edges than blade dicing. Applied to SiC power chips, AlN ceramics, InP photonic dies, and GaAs MMIC chips where blade contact causes micro-cracking at the die edge that degrades electrical isolation and mechanical reliability.

SiC · AlN · InP · GaAsDiamond tip scribingControlled cleaveCrystallographic cleavage guidedNo micro-cracking
Stealth Laser Dicing
Why silicon photonics and MEMS customers choose stealth over blade
Conventional blade dicing floods the wafer with cooling water at high pressure, producing dicing debris (silicon swarf) that contaminates optical waveguide facets, MEMS cavities, and fragile membranes. For silicon photonic PICs, water and particles at the cleaved waveguide facet cause permanent coupling loss. For MEMS with fragile membranes, water surface tension during drying fractures the membrane. Stealth laser dicing modifies only the interior of the silicon, the surface never contacts water or blade.
Dry process, no water spray ever contacts the wafer surface
No dicing debris or silicon swarf generated
No chipping at die edges, interior-only laser modification
Compatible with low-k dielectric device layers (fragile to mechanical stress)
Polygon dies: hexagonal, octagonal, any shape software-defined
Full wafer processed without wet exposure at any step
MEMS fragile membranes, cantilevers, and bridges survive intact
Silicon photonics waveguide facets protected, coupling efficiency maintained
Stealth pattern defined by software, no tooling cost for new die shapes
Enables dicing of fully packaged wafer-level packages after molding
Additional Materials
Metal substrates, large glass, and more
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Metal Substrate Dicing

Dicing of metal substrates and MEMS-on-metal devices, copper foil, stainless steel (SUS), and aluminium sheets. Requires specialist metal-cutting blades different from semiconductor dicing wheels. Applied to flexible circuit singulation, metal-substrate MEMS sensors, and thin-film devices on metal foil where conventional wafer dicing blades would deform the substrate rather than cut it cleanly.

Cu · SUS · AlMetal-specific bladesMEMS on metalFlexible circuit dicingMetal foil devices
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Large-Format Glass Dicing

The most distinctive dicing capability we offer: 300×400mm and 500×600mm rectangular glass substrate dicing for applications that produce many chips per panel. Biochip arrays, display glass singulation, glass interposer panels, and microfluidic chip singulation all require panel-format dicing far beyond what 300mm circular wafer dicing tools can process. Glass-specific cutting parameters prevent the micro-cracking and edge chipping that standard Si blade parameters cause in glass.

500×600mm panels300×400mm panelsBiochip arraysDisplay glass singulationGlass interposer dicing
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Polygon-Shaped Dies

Hexagonal, octagonal, and other non-rectangular die shapes enabled by stealth laser dicing, the laser path is entirely software-defined, so any polygon shape is achievable without tooling. Used for circular optical elements (where a rectangular die wastes chip area), RF antenna chips (where die shape follows the antenna pattern), and die geometries optimized for non-rectangular device layouts or assembly into cylindrical packages.

Hexagon · OctagonAny polygon shapeSoftware-defined pathNo tooling costCircular optical elements
Post-Dicing Services
Inspection, sorting, and tray packing
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Automated Optical Inspection

Post-dicing AOI scans every die for chipping at the kerf edge, surface particles, delamination, and cracks. Map-based sorting identifies and records the position of every defective die before any physical handling occurs. Electro-optical testing available for silicon photonics dies, coupling efficiency measured on-wafer before dicing as part of the known-good-die selection process.

AOI every dieKerf chip detectionMap-based sortingSiPho optical testPre-dicing EO test
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Die Sorting & Known-Good-Die

Sorted die placement by quality grade, known good die (KGD), marginal, and reject, recorded against the wafer map. Dies picked from tape and placed into waffle packs or JEDEC trays according to wafer map coordinates. KGD selection enables downstream flip-chip and die bonding assembly to use only verified good dies, reducing assembly yield loss and avoiding costly post-assembly test of bad die.

KGD selectionWaffle packJEDEC trayMap-coordinate placementYield improvement at assembly
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Tray Packing & Shipment

Singulated dies packed in JEDEC-standard and custom trays with anti-static and anti-humidity measures. Controlled humidity storage and nitrogen-purged sealed bags for compound semiconductor dies sensitive to surface oxidation (InP, GaAs). Traceable packing records, each tray labelled with wafer ID, die count, quality grade, and process data reference. Available for dies from sub-millimetre to large multi-centimetre sizes.

JEDEC traysAnti-static · Anti-humidityN₂ purge for InP/GaAsTraceable recordsAny die size
Dicing Specifications
All methods, substrate and capability overview
MethodSubstrate / SizeDie ShapeAccuracyKey Capability
Blade dicing, Si4–12 inch circularRectangular only±2µm kerfStandard; water-cooled; fast throughput
Blade dicing, Glass4–12 inch; 300×400; 500×600mmRectangular±5µm kerfGlass-specific blade; panel-format unique
Blade dicing, Thick glassAny; up to 500×600mmRectangularInterposer lids; MEMS packages
Stealth laser dicingSi wafers; any sizeAny polygon shapeSub-µmDry; no debris; SiPho; MEMS; polygon dies
Diamond scribingSiC; AlN; InP; GaAsRectangular (cleave-guided)Crystal planesBrittle compound semi; no micro-cracking
Metal dicingCu; SUS; Al sheetsRectangularFlexible circuits; metal MEMS
Large-format glass300×400mm; 500×600mmRectangular±5µmUnique panel-scale capability
Applications
Dicing across every semiconductor market
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Silicon Photonics PICs

Stealth laser dicing of SiPho wafers, preserving optical waveguide facet quality that water-based blade dicing permanently degrades. Clean facets directly after stealth dicing, no additional facet polishing required for many applications. Pre-dicing optical testing identifies KGD before singulation.

Stealth laser · Dry · Waveguide facets clean · SiPho PIC · KGD test
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MEMS Sensors & Actuators

Stealth laser dicing of MEMS wafers with fragile membranes, cantilevers, and suspended structures, water from blade dicing causes membrane fracture by surface tension during drying. Polygon stealth dicing for MEMS with non-rectangular die geometries. Thick handle wafer dicing for MEMS packages.

Stealth laser · MEMS membranes safe · Polygon dies · IMU · Pressure sensor

SiC Power Chips

Diamond scribing of SiC wafers along crystallographic cleavage planes, eliminating the micro-cracking at die edges that SiC blade dicing causes and that degrades high-voltage blocking capability. Applied to SiC MOSFETs, SBDs, and thyristors for EV inverters and industrial drives.

Diamond scribing · SiC cleavage · No micro-cracking · SiC MOSFET · EV inverter
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Biochip & Glass Arrays

Large-format glass dicing (500×600mm) of biochip arrays, singulating hundreds of biochip dies per panel run. Glass-specific dicing parameters prevent micro-cracking of glass channel structures. Quartz and fused silica dicing for DNA sequencing flow cells.

500×600mm glass · Biochip array · Quartz · Fused silica · DNA flow cells
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RF MMIC & mmWave Chips

Diamond scribing of GaAs and InP MMIC chips, avoiding the die-edge micro-cracking that blade dicing causes in III-V compound semiconductors. Clean die edges are critical for RF isolation between adjacent dies in module assembly. Gold-bottom dicing tape prevents metal contamination of compound semiconductor dies.

Diamond scribing · GaAs · InP · MMIC · RF isolation · mmWave
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Consumer IC WLCSP

Standard blade dicing of thinned Si wafers (100–200µm) carrying fan-in WLCSP-packaged ICs. Wafer map-guided sorting separates KGD from marginal and failed dies before tape mounting and tray packing for shipment to module assembly houses.

Blade dicing · Thin Si · WLCSP · KGD sort · JEDEC tray · Mobile/IoT
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Display Glass Singulation

Large-format blade dicing of 500×600mm display glass panels, singulating individual display substrates, sensor arrays, or biochip arrays from the panel. Panel-format dicing achieves dramatically lower cost-per-chip than wafer-format dicing for large substrate applications.

500×600mm blade · Display glass · Panel singulation · Low cost-per-die
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LSPR & Optical Microchips

Stealth laser dicing of LSPR biosensor chips and optical microchip arrays in non-rectangular geometries, hexagonal LSPR chip arrays, circular optical elements, and custom-footprint photonic dies. Software-defined stealth path enables any geometry without tooling cost.

Stealth laser · LSPR chips · Optical elements · Hexagonal dies · Custom polygon
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AR/VR Optical Components

Stealth laser dicing of waveguide combiner chips and micro-optics for AR/VR headsets. Optical waveguide devices require the cleanest possible die edge, any chipping or particle near the coupler causes permanent coupling efficiency loss. Polygon stealth dicing for non-rectangular optical combiner footprints.

Stealth laser · Waveguide combiner · Clean edge · AR/VR · Polygon shape
Why Nanosystems JP Inc.
All four methods, a single project with one point of contact
01

Stealth dicing for SiPho and MEMS

Dry, chip-free stealth laser dicing for silicon photonics PICs and fragile MEMS, the only method that protects optical waveguide facets and MEMS membranes. Unique in Japan for production-scale SiPho dicing.

02

500×600mm large-format glass

Panel-format glass dicing to 500×600mm for display glass, biochip substrates, and glass interposers, far beyond the 300mm circular wafer limit of standard dicing tools. Rare globally.

03

Polygon dies, any shape

Hexagonal, octagonal, and custom polygon dies by stealth laser, software-defined path, no tooling cost, no minimum lot size. New die shape available from the next dicing run.

04

Compound semiconductor expertise

Diamond scribing for SiC, AlN, and InP, materials that chip under standard blade dicing. Crystallographic cleavage plane awareness prevents die-edge micro-cracking that degrades device performance.

05

Full backend service

Dicing, optical inspection, KGD sorting, and JEDEC tray packing, . No separate dicing house and inspection house to coordinate. One delivery with complete die quality records.

06

Coordinated with backgrinding

Wafer thinning (CMP/grinding) and dicing are often sequential steps. Both handled in the same project, one schedule, one PM, one project wafer shipment between thinning and dicing.

Next in your process flow

Wafer Bonding: After dicing individual dies are assembled, wafer bonding is the step for wafer-level 3D integration: hybrid bonding, eutectic, fusion, and anodic bonding.

Wafer Bonding →

Start your project.
Response within 1 business day.

Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.

[email protected] · +81-3-5288-5569 · NDA available

All Services
Full process flow →
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 💡 PhotolithographyE-beam 20nm to 500×600mm 🔬 NanoimprintingUV & thermal NIL 🔵 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA ⚗️ EtchingICP-RIE, DRIE >50:1 🌡️ AnnealingN₂/H₂/vacuum/RTA 🎯 Ion ImplantationB/P/As/Al/N implant 🔶 CMP & GrindingCu CMP, 50µm thinning ✂️ DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 🔓 TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 📐 RDL FabricationBCB/PBO/PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D/2.5D PackagingTSV+RDL+UBM+C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600mm, NIL 🔆 SiPho PackagingTSV·RDL·UBM·C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D/3D 💎 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →
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Services & Industries
⚙️ Capabilities Overview
Substrates
🔷 Substrate & WafersSi, SiC, GaN, glass, sapphire 🔬 Fused Silica WafersQuartz · borosilicate · low CTE 🟣 PI Film & SUS Sensor FabRoll-to-roll · sensor patterning
Front-End
🎭 Mask FabricationGDS to chrome mask, DRC 📷 PhotolithographyE-beam 20 nm to 500×600 mm 🔬 NanoimprintingUV & thermal NIL 🫧 Thin Film DepositionPVD, CVD, ALD, MBE ⬆️ LiftoffMetal pattern · shadow mask ⚡ ElectroplatingCu TSV fill, DPC, LIGA 🌊 EtchingICP-RIE, DRIE >50:1 🔥 AnnealingN₂ / H₂ / vacuum / RTA ⚛️ Ion ImplantationB / P / As / Al / N implant 🔄 CMP & GrindingCu CMP, 50 µm thinning 💎 DicingBlade, stealth laser 🧪 Wafer CleaningRCA, plasma, megasonic
Advanced Packaging
🔗 Wafer BondingHybrid, eutectic, fusion 📌 TSV FabricationHigh AR, void-free Cu fill 👁️ TSV RevealBackgrind → etch → CMP 🪟 TGV FabricationThrough-glass via 🔀 RDL FabricationBCB / PBO / PI + damascene 📦 Packaging & AssemblyWire bond, flip-chip 📚 3D / 2.5D PackagingTSV + RDL + UBM + C4 🥇 AuSn BumpPVD lift-off, fluxless 🧬 Biochip & MicrofluidicsGlass 500×600 mm, NIL 🔆 SiPho PackagingTSV · RDL · UBM · C4 for PIC
Industries
🤖 AI & HPC PackagingCoWoS-style, 2.5D / 3D 💡 Silicon PhotonicsSOI · AuSn · TSV interposer 🚗 AutomotiveMEMS sensors, SiC power 🧬 Life SciencesLab-on-chip, biosensors 🔭 All Industries → Request a Quote →