At Nanosystems JP Inc., we offer a complete range of semiconductor, MEMS, and nano-fabrication processes - from substrate procurement through front-end processes, back-end integration, and final assembly to diced chip, managed under a single project.
| Process | Key Specifications | Substrate / Size |
|---|---|---|
| CORE SEMICONDUCTOR PROCESSES | ||
| Substrate & Wafer Supply | Si, Glass, SiC, GaN, GaAs, InP, InGaAs, Sapphire, Quartz, LiNbO₃ and more | 2″–12″ wafers · glass panels to 550×650mm |
| Design & Mask Fabrication | Chrome-on-glass, quartz masks. GDS/DXF input. DRC + fracturing. | Standard and large-format masks |
| Photolithography | E-beam 20nm · KrF 50nm · i-line stepper 4µm (500×600mm) · Mask aligner · X-ray LIGA | Up to 12″ + panels to 500×600mm |
| Nanoimprinting (NIL) | UV NIL 50nm · Thermal NIL · Large format 500×500mm · Mould fabrication (Si/Ni/quartz) | Up to 500×500mm |
| Thin Film Deposition | PVD (sputtering, e-beam, ion plating) · CVD (LPCVD, PECVD) · ALD · MBE · Roll-to-roll · 100+ materials | Up to 500×600mm |
| Electroplating & Electroforming | Cu/Ni/Au/AuSn electroplating · TSV/TGV fill · LIGA Ni electroforming (1µm features) | Up to 300mm + large panels |
| Etching | ICP-RIE (compound semi, SiC, waveguides) · RIE · DRIE (35:1 AR, Bosch) · KOH/TMAH/BOE wet etch | Up to 12″ |
| Annealing | N₂ · H₂ · Vacuum · RTA up to ~2000°C · SiC Carbon Cap annealing | Up to 12″ |
| Ion Implantation | 20+ dopants · High-temp SiC/GaN (600°C) · H high-conc. implant · RTA to 1800°C | Chips to 300mm |
| CMP & Wafer Grinding | Metal/insulator CMP · SiC/sapphire polishing · Pre-bonding CMP · Backgrinding to 50µm | Up to 12″ |
| Dicing Wafer Cleaning Wafer Cleaning | Blade dicing · Stealth laser (polygon dies, Si photonics) · SiC/InP/GaAs dicing · Inspection + tray pack | Up to 500×600mm |
| ADVANCED PACKAGING | ||
| Wafer Bonding | Hybrid (±1µm) · Thermocompression · Eutectic (AuSn/AuGe) · Fusion · Anodic · Glass frit · PDMS | Chips to 12″ |
| TSV Fabrication | DRIE >100µm · Void-free Cu fill · Oxide liner (PE-TEOS/ALD) · Barrier/seed · CMP | Up to 12″ |
| TSV Reveal | Temporary bonding · Backgrinding · Dry etch reveal · SiN/SiO₂ deposition · CMP | Up to 12″ |
| TGV Fabrication | Via from 20µm · Aspect ratio 1:10 · >95% yield · Cu fill · Both-side RDL · BGV available | Wafers + panels to 510×510mm |
| RDL Fabrication | Polymer passivation (BCB/PBO/PI) + Cu damascene (single + double) · Both-side TGV RDL | Up to 12″ |
| Packaging & Assembly | Die/wire/flip-chip bonding · BEOL · UBM (ENP/ENIG/ENEPIG) · C4 bumping (Cu/CuSn/AuSn) | Up to 12″ |
| AuSn Bump Services (PIC) | PVD multilayer + electroplating · 80/20 standard + custom · Ti/Ni/Au UBM · ENIG/ENEPIG | 4″–12″ incl. cavity wafers |
| SPECIALTY SERVICES | ||
| Biochip & Microfluidics SiPho Wafer-Level Packaging | Glass/Si/polymer chips · PDMS soft litho · Injection moulding · Organ-on-chip · MEA | Glass to 500×600mm |
Share your process requirements, substrate, and production volume, A Nanosystems JP Inc. engineer will respond within 1 business day. Full quote typically within 7–10 business days, subject to project complexity and NDA requirements.